The invention relates to electronic semiconductor devices, and, more particularly, to fabrication methods for such devices.
Semiconductor integrated circuits with high device density require minimum size structures such as short gates and shallow source/drain junctions for field effect transistors ("FET"s), small area emitters for bipolar transistors, and narrow interconnection lines between devices. Short gates and narrow interconnection lines lead to higher resistance for the typical polysilicon gates and first level interconnection lines, and this increases RC time delays and slows circuit operation.
One approach to reduce the resistance of polysilicon gates and interconnection lines uses a self-aligned metal silicide on top of the polysilicon; the metal may be refractory metals such as titanium, cobalt, and nickel. The silicidation process first deposits a blanket film of metal and then reacts the metal with any underlying silicon but not underlying insulator such as silicon oxide (a nitrogen atmosphere may used to simultaneously form the metal nitride to inhibit silicon diffusion). Lastly, the process removes the metal (plus any metal nitride) which did not become silicide. For example, see U.S. Pat. No. 4,821,085 discloses titanium metal and in a nitrogen atmosphere titanium nitride forms.
The removal of metal (and metal nitride) in this self-aligned silicide process requires a very high selectivity with respect to removal of the metal silicide, otherwise the metal silicide will be thinned and lose the advantages of siliciding. For example, the stripping of titanium nitride with the standard basic SC1 solution (12.5% ammonium hydroxide solution, 12.5% hydrogen peroxide solution, and 75% water) at room temperature has a selectivity with respect to titanium silicide of roughly 7.8 to 1. This low selectively presents problems in the known silicide processes.